View HYB39S64160AT_3284265.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

infineon technologies 1 7.99 hyb39s64160a/bt-5.5/-6/-7 64mbit synchronous dram 4m x 16 mbit synchronous dram for high speed graphics applications the hyb39s64160a/bt-5.5/-6/-7 are high speed dual bank synchronous drams based on infineon 0.25 m m (a1-die) and 0.2 m m (b-die) process and organized as 4 banks x 1mb x 16. these synchronous devices achieve high speed data transfer rates up to 183 mhz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with infineon advanced 16mbit dram process technology. the device is designed to comply with all jedec standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of up to 183 mhz is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operate with a single 3.3v +/- 0.3v power supply and are available in tsopii packages. these synchronous dram devices are available with lv-ttl interfaces. ? high performance: ? fully synchronous to positive clock edge ? 0 to 70 c operating temperature ? dual banks controlled by a11 ( bank select) ? programmable cas latency : 2, 3 ? programmable wrap sequence : sequential or interleave ? programmable burst length: 1, 2, 4, 8 -5.5 -6 -7 units fckmax @ cl=3 183 166 143 mhz tck3 5.5 6 7 ns tac3 4.5 5 5.5 ns fckmax @ cl=2 133 125 115 mhz tck2 7.5 8 9 ns tac2 5.4 6 6 ns ? full page(optional) for sequencial wrap around ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read / write control ? dual data mask for byte control ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? 4096 refresh cycles / 64 ms ? latency 2 @ 133 mhz ? latency 3 @ 183 mhz ? random column address every clk ( 1-n rule) ? single 3.3v +/- 0.3v power supply ? lvttl interface ? plastic packages: p-tsopii-54 400mil width
infineon technologies 2 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram ordering information pin description and pinouts: type package description die lvttl-version: hyb 39s64160at-5.5 p-tsopii-54 (400mil) 183mhz 4b x 1mb x 16 sdram a1-die hyb 39s64160at-6 p-tsopii-54 (400mil) 166mhz 4b x 1mb x 16 sdram a1-die hyb 39s64160at-7 p-tsopii-54 (400mil) 143mhz 4b x 1mb x 16 sdram a1-die hyb 39s64160bt-5.5 p-tsopii-54 (400mil) 183mhz 4b x 1mb x 16 sdram b-die hyb 39s64160bt-6 p-tsopii-54 (400mil) 166mhz 4b x 1mb x 16 sdram b-die hyb 39s64160bt-7 p-tsopii-54 (400mil) 143mhz 4b x 1mb x 16 sdram b-die clk clock input dq data input /output cke clock enable ldqm, udqm data mask cs chip select vdd power (+3.3v) ras row address strobe vss ground cas column address strobe vddq power for dqs (+ 3.3v) we write enable vssq ground for dqs a0-a11 address inputs nc not connected ba0, ba1 bank select inputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 18 19 20 21 22 23 24 25 26 27 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc) udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 vdd tsopii-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
infineon technologies 3 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas, we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a11 input level during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organisation: 4m x 16 sdram can = ca7 (page length = 256 bits) in addition to the column address, a10(=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 (=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. ba0,ba1 input level bank select (bs) inputs. selects which bank is to be active. dqx input output level data input/output pins operate in the same manner as on conventional drams. dqm ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. one dqm input it present in x4 and x8 sdrams, ldqm and udqm controls the lower and upper bytes in x16 sdrams. vdd,vss supply power and ground for the input buffers and the core logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity. vref input level reference voltage for sdram versions supporting sstl interface
infineon technologies 4 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram block diagram for hyb39s64160a/bt (4 banks x 1mb x 16 sdram) row decoder memory array bank 0 4096x256 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096x256 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096x256 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096x256 x16 bi t column decoder sense amplifier & i(o) bus input buffer output buffer dq0-dq15 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a7, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqmu dqml row addresses column addresses
infineon technologies 5 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram operation definition all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the most important operation commands. mode register for application flexibility, a cas latency, a burst length, and a burst sequence can be programmed in the sdram mode register. the mode set operation must be done before any activate command after the initial power up. any content of the mode register can be altered by re- executing the mode set command. both banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the following table. operation cs ras cas we (l/u)dqm standby, ignore ras , cas , we and address h x x x x row address strobe and activating a bank l l h h x column address strobe and read command l h l h x column address strobe and write command l h l l x precharge command l l h l x burst stop command l h h l x self refresh entry l l l h x mode register set command l l l l x write enable/output enable x x x x l write inhibit/output disable x x x x h no operation (nop) l h h h x
infineon technologies 6 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length address bus (ax) mode register (mx) operation mode ba0 ba1 m8 m10 m11 m9 m7 mode burst read / burst write 0000000 single write burst read / 00 0 1 00 0 burst type m3 type sequential interleave 0 1 m6 m5 m4 latency cas latency 000 reserved 00 1 reserved 0 1 0 2 0 11 3 1 00 1 0 1 11 0 reserved 111 address input for mode set (mode register operation) 1 1 1 1 0 0 0 0 m2 1 2 reserved 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 m1 0 m0 8 4 length burst length sequential interleave reserved full page*) 1 2 4 8 sps03409 *) optional
infineon technologies 7 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner.during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. the power on voltage must not exceed vdd+0.3v on any of the input pins or vdd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 m s is required followed by a precharge of both banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is divided into 4 fields. a burst length field to set the length of the burst, an addressing selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a cas latency field to set the access time at clock cycle and a operation mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. the mode set operation must be done before any activate command after the initial power up. any content of the mode register can be altered by re-executing the mode set command. all banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 133 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature in this device. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is 2, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequential burst type and page length is a function of the i/o organisation and column addressing. full page burst operation do not self terminate once the burst length has been reached. in other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command.
infineon technologies 8 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram similar to the page mode of conventional drams, burst read or write accesses on any column address are possible once the ras cycle latches the sense amplifiers. the maximum tras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be done between different pages. burst length and sequence : refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 full page (optional) nnn cn, cn+1, cn+2,..... not supported
infineon technologies 9 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram the chip has an on-chip timer and the self refresh mode is available. it enters the mode when ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one trc delay is required prior to any access command. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). suspend mode during normal access mode, cke is held high enabling the clock. when cke is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the device cant remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by taking cke ?high. one clock delay is required for mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock before the last data out for cas latencies 2 and two clocks for cas latencies 3. if cas10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation on clock after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes require a time delay twr from the last data out to apply the precharge command.
infineon technologies 10 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram bank selection by address bits : burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1 x x all banks
infineon technologies 11 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram absolute maximum ratings operating temperature range......................................................................................... 0 to + 70 c storage temperature range..................................................................................... C 55 to + 150 c input/output voltage .............................................................................. C 0.5 to min(vcc+0.5, 4.6) v power supply voltage vdd / vddq.......................................................................... C 1.0 to + 4.6 v power dissipation............................................. ............................................................... ...........1 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operation and characteristics : t a = 0 to 70 c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v notes: 1. all voltages are referenced to vss. 2. vih may overshoot to vdd + 2.0 v for pulse width of < 4ns with 3.3v. vil may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit notes min. max. input high voltage v i h 2.0 vdd+0.3 v 1, 2 input low voltage v i l C 0.3 0.8 v 1, 2 output high voltage ( i out = C 4.0 ma) v oh 2.4 C v output low voltage ( i out =4.0 ma) v ol C0.4v input leakage current, any input (0 v < v i n < vddq, all other inputs = 0 v) i i (l) C 5 5 m a output leakage current (dq is disabled, 0 v < v out < vdd ) i o(l) C 5 5 m a parameter symbol values unit min. max. input capacitance (clk) c i 1 2.5 3.5 pf input capacitance (a0-a12, ba0,ba1,ras , cas , we , cs , cke, dqm) c i 2 2.5 3.8 pf input / output capacitance (dq) c i o 4.0 6.0 pf
infineon technologies 12 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram operating currents (t a = 0 to 70 o c, vcc = 3.3v 0.3v (recommended operating conditions unless otherwise noted) notes: 3. these parameters depend on the cycle rate and these values are measured at the maximum specified operation frequency. input signals are changed once during tck, excepts for icc6 and for standby currents when tck=infinity. 4. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vddq current is excluded. parameter & test condition symb. - 5 . 5 - 6 - 7 note max. operating current trc=trcmin., tck=tckmin. ouputs open, burst length = 4, cl=3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access icc1 160 150 145 ma 3 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) tck = min. icc2p 222ma3 tck = infinity icc2ps 111ma3 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) tck = min. icc2n 55 50 45 ma 3 tck = infinity icc2ns 555ma3 no operating current tck = min., cs = vih(min), active state ( max. 4 banks) cke>=vih(min.) icc3n 55 50 45 ma 3 cke<=vil(max.) icc3p 888ma3 burst operating current tck = min., read command cycling icc4 140 130 120 ma 3,4 auto refresh current tck = min., auto refresh command cycling icc5 160 150 145 ma 3 self refresh current self refresh mode, cke=0.2v icc6 111ma3
infineon technologies 13 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram ac characteristics 1)2) t a = 0 to 70 c; v ss = 0 v; v cc = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit -5.5 -6 -7 minmaxminmax clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 5.5 7.5 C C 6 8 C C 7 9 C C ns ns clock frequency cas latency = 3 cas latency = 2 t ck C C 183 133 C C 166 125 C C 143 115 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac C C 4.5 5.4 C C 5 6 C C 5 6 ns ns 2, 3 clock high pulse width t ch 2 C 2 C 2.5 C ns clock low pulse width t cl 2 C 2 C 2.5 C ns transition time t t 0.5 10 0.5 10 0.5 10 ns setup and hold times input setup time t is 1.5C2C2Cns 4 input hold time t ih 1C1C1Cns 4 cke setup time t cks 1.5C2C2Cns 4 cke hold time t ckh 1C1C1Cns 4 mode register set-up time t rsc 11C12C24Cns power down mode entry time t sb 05.50607ns common parameters row to column delay time t rcd 15C16C18Cns 5 row precharge time t rp 15C16C18Cns 5 row active time t ras 33 C 36 100k 42 100k ns 5 row cycle time t rc 49.5 54 C 63 C ns 5 activate(a) to activate(b) command period t rrd 11C12C14Cns
infineon technologies 14 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram cas (a) to cas (b) command period t ccd 1 C1C1Cclk refresh cycle refresh period (4096 cycles) t ref C64C64C64ms self refresh exit time t srex 10 C 10 10 ns read cycle data out hold time t oh 2 C 2 C 2.5 C ns 2 data out to low impedance time t lz 0C0C0Cns data out to high impedance time t hz 25.52627ns dqm data out disable latency t dqz C2C2C2clk write cycle write recovery time t wr 2C2C2Cclk dqm write mask latency t dqw 0C0C0Cclk write latency t wl 0C0C0Cclk parameter symbol limit values unit -5.5 -6 -7 minmaxminmax
infineon technologies 15 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram frequency vs. ac parameter relationship table: -5.5 -parts -6 -parts -7 -parts: cl trcd trp trc tras trrd tccd wl twr 183 mhz 3 3 3 9 6 2 1 0 2 133 mhz 2 2 2 7 5 2 1 0 2 cl trcd trp trc tras trrd tccd wl twr 166 mhz 3 3 3 9 6 2 1 0 2 125 mhz 2 2 2 7 5 2 1 0 2 cl trcd trp trc tras trrd tccd wl twr 143 mhz 3 3 3 9 6 2 1 0 2 115 mhz 2 2 2 7 5 2 1 0 2
infineon technologies 16 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram notes for ac parameters: 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.5 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shown in fig.1. specified tac and toh parameters are measured with a 30 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v.. 3. if clock rising time is longer than 1 ns, a time (t t /2 - 0.5) ns has to be added to this parameter. 4. if tt is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 5. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. fig.1 50 pf i/o measurement conditions for tac and toh sps03410 output v w 50 pf 30 50 w = z tt + spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
infineon technologies 17 hyb39s6416a/bt-5.5/-6/-7 64mbit synchronous dram package outlines: gpx09039 22.22 0.13 1) 127 54 28 0.35 +0.1 -0.05 0.1 1 0.1 10.16 0.13 0.2 11.76 0.1 0.5 does not include plastic or metal protrusion of 0.15 max per side 1) 54x 0.05 0.05 0.15 -0.03 +0.06 15? 5? 15? 5? 6 max 2.5 max 2) 3) does not include plastic protrusion of 0.25 max per side 2) does not include dambar protrusion of 0.13 max per side 3) index marking 0.8 20.8 26x 0.8 = 0.2 m 54x plastic package p-tsopii-54 (400 mil, 0.8 mm lead pitch) thin small outline package, smd
infineon technologies 18 7.99 hyb39s64160a/bt-5.5/-6/-7 64mbit synchronous dram data sheet change list: 8.7.1999 first rev.

▲Up To Search▲

Price & Availability of HYB39S64160AT

	To Download HYB39S64160AT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .